D o c u m e n t a t i o n
Apple I/O Notes
"They don't publish specs for Apple designed chips
outside of Apple unless your a major business partner,
and it's in Apple's best interests to do so."
pci: bandit (343S1126) apple-io: bandit/ohare (bandit@F2000000/ohare: dbdma) pmu: bandit/ohare/via-pmu kbd: bandit/ohare/via-pmu/adb/keyboard mouse: bandit/ohare/via-pmu/adb/mouse screen: bandit/chips655 scsi: bandit/ohare/mesh ata: bandit/ohare/ata
|Apple I/O: ADB, Mesh SCSI, SCC, AMIC (GC, O'Hare, MPIC, etc.), VIA|
A c r o n y m s
M a i n L o g i c B o a r d
All the I/O interfaces and the video display system are on the main logic board. The controller ICs on the main logic board are connected to the NuBus/PCI bus, which also communicates with the processor module.
Grand Central I/O - 343S1125-03 chip. O'Hare I/O - 343S0172-b chip. Curio I/O (PowerMac 8100/80) Heathrow Mac I/O (G3) Paddington Mac I/O (iMac, PCI G4) The Paddington ASIC is an integrated I/O controller and DMA engine for use in Power Macintosh computers with a PCI bus. The Paddington IC contains the PCI bus arbiter. It also provides the interface and control signals for: - the video display subsystem - the built-in modem - the infrared link - the Ethernet port - the sound ASIC - the internal IDE hard drive - the internal CD-ROM drive - the power manager IC The Paddington IC is similar to the Heathrow IC used in the Power Macintosh G3 computers and Macintosh PowerBook G3 computers. The main difference is that the Paddington IC supports 100Base-TX Ethernet as well as 10Base-T. All mac-io's before KeyLargo are at $Fx000000, KL is at $80000000. On the Macintosh Portable computer, the power-management hardware is the 50753 microprocessor (known as the Power Manager integrated circuit or Power Manager IC). KeyLargo Mac I/O (IBM MPIC Interrupt Controller), UniNorth AGP (G4 Cube, AGP G4, eMac) K2 I/O (IBM MPIC, not MPIC-2, Interrupt Controller) (G5) The AMIC - Apple Memory Mapped I/O Controller - controls most I/O on the Power Macintosh Systems. It performs the following functions: - Handling of interrupts received through the VIA channels; - The SWIM III floppy controller; - DMA for Ethernet, serial communications, SCSI, sound I/O; - Support for onboard video.
A p p l e c h i p s
DS8935(WM) - LocalTalk Dual Driver/Triple Receiver
1. P/N 343S1202-02: The PowerPC to PCI Bridge and Memory controller called "PSX". 2. P/N 343S0172-b: The I/O and DBDMA Controller called "O'Hare". Note: in the 4400 Developer Note, the PCI Bridge ASIC is called "PSX"; in the 6500/5500 Developer Note it is called "PSX+".
1. There are two basic ADB systems. There is the old MacII-class system, and then there is the 68HC05-based. The 68HC05 is masked with a ROM that controls the ADB per instructions from the 6522 VIA. 68HC05 is also in PowerMacs. Apple have buried it deep in the core of some large IC. 68HC05 chip is in charge of power management on the platforms that have it.
2. "Cuda (OldWorld: beige & black macs), PMU (NewWorld: colorful macs)" is not a valid split. Originally the distinction was: PMU for PowerBooks, Cuda (68HC05PG) for desktops. PMU can deal with battery charger, uses a different protocol, has a PWM for backlight control (on some machines), etc... In the New World era, Apple just started calling it "the PMU" regardless of whether the machine is a portable or not. PMU for PowerBooks is quite different from the Core99 one. Newer machines (since Core99) have PMU99 which is not a 68HC05 any more. "The new one just has lots of i2c busses & IOs".
3. >> Cuda, PMU, PMU99: "Those things may be quite different on various families of machines." Core99 boxes: PMU99 replaces Cuda. PMU99 is a Mitsubishi M16C/62F microprocessor. (They uses a different protocols on the 6522 VIA wires.) Apple says the PMU99 is different (not Cuda) and is in a physically different location on the logic board. The Cuda Chip is connected to the Shift Register of the 6522 VIA and to port B, like the PMU99 mostly. Old/new PMUs shares the same protocol to the host (though with some different messages for a few things). PMU doesn't have a TIP bit. (Cuda does.) Cuda, PMU: the message format is different (requires a big table of message lenghts). On PMU99 you don't get the "event" interrupt from CB1 typically, but from a separate GPIO wired to KeyLargo.